1. Field of the Invention
The present invention relates generally to reducing phase noise and distortion in the conversion of an analog video signal to a digital video signal. In particular, the present invention is directed to technology that reduces phase noise and distortion in the digitally converted image by selectively capturing reference frames of the image in accordance with a change threshold.
2. Background Information
Presentations using multimedia projection display systems have become popular for purposes such as sales demonstrations, business meetings, and classroom sessions. In a common mode of operation, multimedia projection display systems receive analog video signals from a multimedia device such as a personal computer (PC). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control a digitally-driven display object, such as a transmissive liquid crystal display (LCD) or digital mirror device (DMD), to form the display images for projection onto a display screen.
Two common types of multimedia projection display systems are LCD projectors and LCD projection panels. An LCD projector includes a transmissive LCD, a light source, and projection optics to form and project display images in the manner described above. An LCD projection panel includes a similar transmissive LCD to form the display image, but operates with a conventional overhead projector (OHP) having a light source and projection optics, to project the display image onto a display screen. Examples of such LCD projectors and LCD projection panels are sold under the respective trademarks LITEPRO and PANELBOOK by In Focus Systems, Inc. of Wilsonville, Oreg., the assignee of the present application.
Because the LCDs and DMDs used in multimedia projection display systems require digital video signals, the multimedia projection display system normally has an analog to digital (A/D) signal converter for converting the PC-generated analog video signals into a digital format suitable for driving the LCD, DMD or other type of display object.
The PC-generated analog video signal is actually comprised of three analog image data signals, one for each of the primary colors, red, green and blue, and a digital timing signal, which may include a pulsed horizontal synchronizing signal (Hsync) as well as a pulsed vertical synchronizing signal (Vsync), or a composite sync signal. The individual analog image data signals representing the colors are generated from bit data in a memory portion of the PC, using three digital-to-analog (D/A) converters, one for each of the colors, red, green, and blue.
A complete image is typically displayed during a time interval known as a “video frame period.” With reference to FIG. 4, each video frame 9 is usually produced to have a central active video region 11 surrounded by an inactive (“blanked”) margin 13. The central active video region 11 is composed of a number of horizontal and vertical picture elements (pixels), typically ranging from 640×480 pixels to 1600×1200 pixels, referred to as the display resolution mode. As the image changes the pixels are activated on and off, with the central active video region 11 being refreshed at rates of 60 to 100 Hz, as dictated by the constraints of the display object (e.g. the LCD, DMD, etc.) used in the multimedia projection display system. Since compatibility with the various PC display resolution modes is a desirable feature for multimedia projection display systems, the A/D signal converter typically includes an interface that is capable of converting analog video signals having a variety of resolution modes.
The A/D signal converter is usually combined with a phase-locked loop (PLL), which may comprise a phase comparator, a low-pass loop filter, and a voltage-controlled oscillator (VCO) formed in a loop to generate a feedback signal that locks into the Hsync pulsed horizontal synchronizing signal. In order to generate a selected multiple n of pixel clock pulses for each period of Hsync, a divide-by-n counter is added to the feedback loop between the VCO output and the phase comparator.
An example of a pixel clock waveform 4 is shown in FIG. 1. The number n of individual pixel clock pulses per Hsync pulse may be set by reference to the resolution mode of the analog video source. To set the resolution mode, certain characteristics of the analog video signal, such as Hsync and Vsync, may be used to refer to a resolution mode look-up table stored in the projection display system's CPU. The number n should be set to equal the number of pixel data components in each horizontal line of the scanned analog signal, including those in the central active video region 11 and the blanked margin regions 13 (see FIG. 4) on either side of the central active video region 11. For example, for a screen resolution of 640×480, the number n may be set at about 800 to include the blanked regions 13 on either side of the 640 pixel-wide central active video region 11. Thus, the pixel clock would sample the continuous stream of analog image data 800 times along each horizontal line of the frame.
FIG. 1 further shows the desired relationship between the analog video data signal 1 and the pixel clock signal 4. The number n of pixel clocks 5 is set to establish a one-to-one relationship between pixel clock pulses 5 and pixel data components 2 of the analog data signal 1. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video data signal frequency. Under this relationship, each pixel data component 2 of the analog signal is sampled by a single pixel clock pulse 5, which reads the instantaneous voltage value of the pixel data component so that it can be digitized. The stream of digitized instantaneous voltage values form the digital video data signal, which is addressed to the LCD, DMD, or other type of display object, to appropriately set pixels to blank (black) or to selected activated (non-black) status to replicate the image defined by the analog video data signal.
One problem with the above-described A/D conversion is that it is often imperfect due to errors in the pixel clock sampling of the analog signal. With reference to FIG. 1, since the pixel clock pulses 5 have “jitter” zones 6 at their leading and trailing edges, the clock pulses 5 should be registered with the centers of the pixel data components 2, so that the sampling is not randomly pushed by the jitter into the transition regions 3 of the analog video data signal 1. If the pixel clock pulses 5 are not properly registered, the resulting sampling imprecision gives rise to frequency (also know as “tracking”) and “phase” errors, both of which introduce noise that may degrade the quality of the LCD, DMD, or other display object's image.
FIG. 2 illustrates a tracking error that results from the improperly setting of the number n of pixel clocks. As discussed above, the number n of pixel clocks should be equal to the number of pixel data components 2 of each horizontal line of analog video data signal 1. As illustrated, the improper setting of n results in the pixel data components 2 not being sampled at a consistent point. Specifically, n is set too large in clock signal 4′ (i.e. the clock signal frequency is too high). The resulting crowding of the pixel clock pulses 5′ yields an additive leftward drift of the pixel clock pulses 5′ relative to the pixel data components 2 of the analog video data signal 1. Such drift causes sampling in the transition regions 3. For instance, as indicated by positional bracket A, the leading edges 7′ of the third through the sixth clock pulses 5′ sample in transition zones 3 of the analog video data signal 1. Accordingly, the transition zone data will be erroneous and the image information from adjacent non-sampled pixel data components 2 will be missing from the digitized video signal. If n is erroneously set large enough, the pixel clock pulses may be so crowded that individual analog pixel data components 2 may be double-sampled. On the other hand, if n is erroneously set too small (i.e. the pixel clock signal frequency is too low), the dispersion of the pixel clock pulses results in a rightward drift wherein sampling may also occur in the transition regions. In all of these cases, the erroneous sampling provides erroneous video signal data that generates unwanted distortion that degrades the LCD or other display object video image quality.
FIG. 3 illustrates that phase error may occur even when the pixel clock signal frequency equals the analog video data signal frequency (i.e. even when there is no tracking error). For example, as shown in pixel clock signal 4″ in FIG. 3, the clock phase may be erroneously set such that every pixel clock pulse samples a transition region 3 of the analog video data signal. Leading edge jitter makes such phase error more likely, since if the jitter zones 6″ straddle the intersections 8 of the pixel data components 2 and transition regions 3 of the analog video data signal 1, the voltage will be randomly sampled on either side of the intersection 8. In any case, phase error is undesirable since it generates unwanted phase noise, or “snow” in the LCD, DMD, or other display object video image.
Prior art techniques for reducing noise have focused on providing feedback to the pixel clock in order to eliminate the above-described tracking and phase errors. For example, a current projection display system may include an image capture circuit that automatically eliminates phase and tracking errors by monitoring the actual active image width of the analog video data signal measured by the number n of pixel clocks, and adjusting the frequency and phase components of the pixel clock signal until the expected width of the image matches the actual width. A current projection display system may also include an image capture circuit that automatically eliminates phase and tracking errors by monitoring a selected pixel data component at the edge of the central active video region that is horizontally stationary from frame to frame of the analog video data, and automatically iteratively adjusting the pixel clock pulse until a pixel clock pulse is centrally registered with the selected pixel data component. Both of these prior art techniques used in current projection display systems are described in U.S. Pat. Nos. 5,767,916 and 5,805,233, assigned to In Focus Systems, Inc. of Wilsonville, Oreg., the assignee of the present invention.
The image capture circuit of a current projection display system includes a programmable delay device, a PLL, a divide-by-n-counter, an A/D converter, and an ASIC (Application Specific Integrated Circuit) that contains the image edge or width detection circuitry that provides the feedback necessary to correct the pixel clock.
In operation, the A/D converter samples (reads) the instantaneous voltage value of the analog video data signal at the leading edge of each of the pixel clocks, thereby generating a series of sampled data signal values. The A/D converter then quantizes the sampled values by matching each value to one of a series of preselected voltage amplitude levels, which have corresponding numerical values. The numerical values are represented digitally and coded to establish 8-bit data for each of the colors, red, green, and blue. The three eight-bit color data signals are input through the three respective color data signal channels to the ASIC. A window random access memory (WRAM) is connected between the ASIC and the LCD, DMD, or other display object that ultimately receives the output from the A/D converter. At the display object, the coded color data signals set pixels to blank (black) or to specific activated (non-black) status corresponding to the sampled voltage level. A microcontroller, which is part of the current projection display system CPU, uses the feedback provided by the ASIC to control the programmable delay device and divide-by-n-counter to change the pixel clock settings and eliminate the phase and tracking errors.
Despite the above-described improvements in eliminating phase and tracking errors, current projection display systems are still not optimum. Particularly frustrating is the fact that the causes of the phase noise and distortion may dynamically change as the environment changes. Thus, any given technique for reducing or eliminating the distortion may or may not be effective from one moment to the next.
Another problem is that a digitized video frame representing the complete image displayed during the video frame period must be stored within the WRAM until it is transmitted to the display object. Since the video frames are typically stored in WRAM at a faster rate than they are transmitted to the display object, the WRAM must include enough frame buffer capacity or memory to store a number of video frames at once. For example, each video frame may be stored to the WRAM at the rate of 80 Hz (i.e. 80 frames per second), but may only be output to the display object at the rate of 60 Hz, as dictated by the refresh rate of the particular display object (e.g. the LCD, DMD, etc.).
For even the lowest resolution video display systems, storing video frames in WRAM results in the storage of a significantly large amount of data. Since a video frame represents the complete image, it contains data representing every pixel in the central active video region. The optical state of each pixel in the central active video region, i.e. its color or shade of gray, is described by several bits of data; the exact number of bits depends upon the desired number of colors or shades of gray that are to be displayed. For example, a typical LCD may have 480 rows and 640 columns that intersect to form a matrix of 307,200 pixels corresponding to the pixels in the central active video region. Consequently, if 8 bits are required to specify each of the three colors comprising each pixel, then 921,600 bytes of image data (3 bytes×307,200 pixels), or nearly 1 megabyte, are required to characterize a single digitized video frame.
The problem of having to provide a necessarily large WRAM storage capacity is compounded by the fact that the WRAM is expensive, which adds significantly to the cost of the multimedia projection display system. Additionally, the WRAM takes up a large amount of board space. Moreover, the sheer volume of digitized video frames generated by the multimedia projection display system requires a significantly large transmission bandwidth between the WRAM and the LCD, DMD, or other display object. Large transmission bandwidth requirements present a problem when designing networked presentation projector applications. For example, in a wireless network environment, including wireless networks designed in accordance with the IEE 802.11 Wireless LAN Standard, or the Draft Specification of Bluetooth: A Global Specification for Wireless Connectivity, promulgated by the Bluetooth Special Interest Group, or even in a conventional networked environment where the LCD, DMD, or other display object is capable of providing its own frame memory, it is desirable to reduce the transmission bandwidth requirements where possible to enable the development of networked presentation projector applications.
Accordingly, it is desirable to provide a multimedia projection display system that not only reduces the noise and distortion in the digitally sampled image, but also reduces the transmission bandwidth requirements between the WRAM and the display object.